# 數位電路設計高手請進

I read two books to look for the correct answer of how the clock skew affects the minimum clock period. Those two books give me different answers!! Imagine that we have two registers with a combinational logic between them.

Book1 (Digital Integrated Circuits, by Rabaey) says that the minimum bound on clock period is (T) >= (Tr,max) plus (Ti) plus (Tl,max) minus (Tskew)......where Tr,max is the maximum delay of the register, Ti is the wire delay, Tl,max is the maximum delay of the combinational logic and Tskew is the clock skew. (Here Rabaey probably ignore the Tsetup, the setup time of the register.) Rabaey says that positive skew increases the throughput of the circuit because the clock period is shortened by Tskew. Whereas negative skew impacts the throughput.

Appendix in Book2 (Computer Organization and design by Hennessy and Patterson) says that the clock period must be longer than

(Tprob) plus (Tcombinatorial) plus (Tsetup) plus (Tskew)...where Tprob is the delay of the flip-flip, Tcombinatorial is the delay of the combinational logic, Tsetup is the setup time of the flip-flip and Tskew is the clock skew. Here the clock skew is positive.

Two different answers!! Who tells the truth?

(系統 show 不出加號???)

One gives me -Tskew in the clock period and the other gives me +Tskew

### 1 個解答

• 匿名使用者
2 0 年前
最佳解答

case1: take two flops clocked by same clock source. if clock to flop2 is skewed or delayed with respect to Flop1 then it is positive skew. clock period> propagation of flop1 + wire delay+ tsetup of flop2 - tskew this is called + ve skew since it increases throughput or maximum freq of operation. if u c this skew reduces the set up requirements of flop2. case2: if clock to flop1 is skewed with respect to flop2 then it will increase the propation delay of data through flop1 which will reduce the through put or frequency of operation. hence called negative skew. clockperiod > propFF1+ wiredelay+ tsuFF2 + clockskew