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rita 發問時間: 社會與文化語言 · 1 0 年前

請各位見義勇為的大俠協助幫忙翻成中文

Chip or Die: Tiny, thin, square individual semiconductor device with a fabricated electronic circuit.

Lead Frame: Metal where the Chip is directly attached or the Wire is directly connected.

Ag Epoxy: Conductive resin with properties of silver (Ag) to attach the Chip to the Lead Frame

Polyimide Tape: Adhesive tape for attaching the Chip to be worked into the LOC package to the Lead Frame

Au Wire: Thin wire purity of 99.999% or more for connecting the chip pad and Lead

Mil: Unit of length, the value of which is obtained by diving 1 inch by 100(1inch/1,000=0.254mm=25.4um=1mil)

上面這些是名詞定義,請幫忙幫我翻成中文,謝謝~

Defects Found in sawing process

a. Chip out / Chip crack

When the outermost metal line is attached, it is defect.

b. Sawing Misalignment

If the metal portion is sawed or if the outermost oxide film is sawed, it is defect.

c. Contamination

It is defect if there is contamination due to ion such as fingerprints.

It is also defect if it is possible to observe the contamination on the Bond Pad with Microscope of 50X and Characteristics Test is conducted (Pull,Ball Shear) and criteria of such Test shall be applied.

Defect Found in Die Attachment Process

a. Epoxy on chip: it is Die Epoxy is on the Chip, it is defect. However, for the coated device, it is defect only if the epoxy exists on the area stripped of the coating ( Bond Pad, Fuse) within the coated areas.

b. Epoxy on lead: if the Die Epoxy touches the Stitch Bond of the Lead or if it exists on the area to be plated during the plating process, it is defect.

c. Die Placement: if the Die gets out of the Pad Mount of the Lead Frame or if it differs from the Pad position as indicated in the Bonding drawing, it is defect.

d. Die Orientation

e. No Die: it is defect if there is no Chip on the Pad Mount of the Lead Frame.

f. Chip out / Chip Crack: 1.Top Side: it is defect if the outermost Metal Line is attacked.

2 個解答

評分
  • 1 0 年前
    最佳解答

    Chip or Die: 晶片,晶粒 : 微小的,薄的,方型的積體電路半導體元件。

    (一般chip 與 die還是有分,chip 多指切割後,未封裝, die多指未切割,但大多混用)

    Lead Frame:花架: 裝配晶片用之金屬帶狀引導框架。

    Ag Epoxy: 銀膠: 以銀為導體所製作的導電銀膠,作為晶片與花架間之導通與貼合之材料。

    Polyimide Tape: 聚醯胺膠帶: 以聚醯胺所製成的膠帶,可作為貼合晶片與lead-on-chip花架的封裝之材料。

    Au Wire: 金線: 以99.9999%純度的黃金所拉製而成,作為晶片上的焊墊與引腳間的連接線。

    Mil: 密爾: 長度單位,值為千分之一英吋。

    上面這些是名詞定義,請幫忙幫我翻成中文,謝謝~

    Defects Found in sawing process

    晶圓切割所發現的缺陷

    a. Chip out / Chip crack

    晶片出界?? /晶片破損

    When the outermost metal line is attached, it is defect.

    當最外圍的金屬導線被貼合?? 視為缺陷

    b. Sawing Misalignment

    切割錯位 (位置度不準)

    If the metal portion is sawed or if the outermost oxide film is sawed, it is defect.

    如金屬導線部分或外圍氧化層被切割視為缺陷

    c. Contamination

    污染

    It is defect if there is contamination due to ion such as fingerprints.

    如有離子污染,甚至指印等視為缺陷

    It is also defect if it is possible to observe the contamination on the Bond Pad with Microscope of 50X and Characteristics Test is conducted (Pull,Ball Shear) and criteria of such Test shall be applied.

    如於50倍顯微鏡下觀察可發現鋁墊上之污染視為缺陷,但因測試所產生的扎痕不在此限

    Defect Found in Die Attachment Process

    a. Epoxy on chip: it is Die Epoxy is on the Chip, it is defect. However, for the coated device, it is defect only if the epoxy exists on the area stripped of the coating ( Bond Pad, Fuse) within the coated areas.

    晶片殘膠污染: 晶片上存有殘膠污染, 視為缺陷,然而如晶片已經過塗佈處理,則殘膠如存在於鋁墊,保險絲上者才視為缺陷

    b. Epoxy on lead: if the Die Epoxy touches the Stitch Bond of the Lead or if it exists on the area to be plated during the plating process, it is defect.

    引腳殘膠污染: 引腳上存有殘膠污染,或預備電鍍區域有殘膠污染視為缺陷

    c. Die Placement: if the Die gets out of the Pad Mount of the Lead Frame or if it differs from the Pad position as indicated in the Bonding drawing, it is defect.

    晶片錯置: 晶片位置與花架所規劃之位置不符,或鋁墊位置與打金線之規劃位置不符視為缺陷

    d. Die Orientation

    晶片方向

    e. No Die: it is defect if there is no Chip on the Pad Mount of the Lead Frame.

    無晶片: 花架上無晶片視為缺陷

    f. Chip out / Chip Crack: 1.Top Side: it is defect if the outermost Metal Line is attacked.

    以上是參考半導體用語辭典&自己的一些判斷,希望沒有錯誤,如果各位先進發現錯誤,請不吝指正,Thanks!(有??代表我不確定,請其他人協助)

    參考資料: 半導體用語辭典&自己
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  • 1 0 年前

    前面是說名詞

    晶片(Die或Chip)

    支架 導線架Lead Frame

    銀膠Ag Epoxy

    Polyimide Tape 不會

    Au Wire金線打線導通用外加散熱

    Mil買金線都用這單位1.0 1.2 1.5Mil

    總之在支架上面點銀膠在固晶-----固晶

    烤完後在晶片跟支架上打線導通---銲線

    下面的文章

    晶片的QC程序

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