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匿名使用者 發問時間: 社會與文化語言 · 1 0 年前

看不懂得文章可以翻一下嗎

Fig. 4 shows the circuit block diagram of the configuration of the proposed FPGA-based HEPWM generator. In this work, eight switching patterns related to the cases of M=3, M=5,…,and M=17 are stored in the EPROM. The switching patterns can be encoded by cascading the digitized signals of the modulation index and phase angle as address inputs for the EPROM. In addition, to synthesize the circuit functions on an FPGA, the timing management is essential.

As illustrated in Fig. 5, the timing control circuit consists of READ timing control as well as synchronous input for EPROM, and dead-time control for lockout circuit. The access time, a measure of EPROM’s operation speed, should be programmed on the FPGA (EPM7128SLC84-15) to enable the READ operation of the EPROM. The output frequency of the oscillator-I in Fig. 4 is regarded as the time reference in order to create the access time, the dead-time, and the synchronous time for the FPGA. The sequences of timing circuits are carried out in the syntax of the finite state machine (FSM).

大大們幫忙翻一下~看不懂可以翻成中文嗎??

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  • 1 0 年前
    最佳解答

    圖4 演出被提議的基于FPGA的HEPWM 發電機的構造的電路方框圖。 在這工作裡, 與M = 3,M = 5的情況有關的8 種接通的圖案,K 和M = 17被儲存在EPROM裡。 接通的圖案可能透過為EPROM串聯被數字化的調製索引和相位角的信號作為位址輸入被譯成代碼。 另外,為了在FPGA上合成電路功能,時間管理是必要的。 象在圖5 說明的那樣, 時間控制電路由讀定時控制和同步輸入給EPROM,和死時間控制適合停業周組成。 存取時間,一個EPROM s 操作速度的度量標準,應該被在FPGA(EPM7128SLC84-15)上編程式使EPROM的讀出操作成為可能。 o 為了存取時間創建,在圖的振蕩器的utput 頻率-I 4被認為是時間參考, 滯留時間, 以及FPGA的同步時間。 定時電路的順序被在有限狀態機(FSM)的句法方面進行。

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