# verilog 編譯問題

module IC_7447(in3, in2, in1, in0, out);

input reg in0, in1, in2, in3;

output reg [6:0] out;

initial

begin

out = 0;

#10 {in3, in2, in1, in0} = 2'd0;

#10 {in3, in2, in1, in0} = 2'd1;

#10 {in3, in2, in1, in0} = 2'd2;

#10 {in3, in2, in1, in0} = 2'd3;

#10 {in3, in2, in1, in0} = 2'd4;

#10 {in3, in2, in1, in0} = 2'd5;

#10 {in3, in2, in1, in0} = 2'd6;

#10 {in3, in2, in1, in0} = 2'd7;

#10 {in3, in2, in1, in0} = 2'd8;

#10 {in3, in2, in1, in0} = 2'd9;

#10 \$finish;

end

always @({in3, in2, in1, in0})

case( {in3, in2, in1, in0} )

2'd0: out = 1111110;

2'd1: out = 0110000;

2'd2: out = 1101101;

2'd3: out = 1111001;

2'd4: out = 0110011;

2'd5: out = 1011011;

2'd6: out = 0011111;

2'd7: out = 1110000;

2'd8: out = 1111111;

2'd9: out = 1110011;

default: out = 7'bx;

endcase

endmodule

# ** Error: C:/altera/code/7447.v(2): Port mode is incompatible with declaration: in0

# ** Error: C:/altera/code/7447.v(2): Port mode is incompatible with declaration: in1

# ** Error: C:/altera/code/7447.v(2): Port mode is incompatible with declaration: in2

# ** Error: C:/altera/code/7447.v(2): Port mode is incompatible with declaration: in3

7447.v(2): Port mode is incompatible with declaration: in0

7447.v(2): Port mode is incompatible with declaration: in1

7447.v(2): Port mode is incompatible with declaration: in2

7447.v(2): Port mode is incompatible with declaration: in3

2 個已更新項目:

### 3 個解答

• 1 0 年前
最佳解答

大大妳好

必須先告訴你一個很基本的概念

你在input的地方把input給宣告成reg

這是錯誤的

在設計模組區塊紙可以把output給宣告成reg

所以首先第二行應該要改成這樣

input reg in0, in1, in2, in3; --> input in0, in1, in2, in3;

initial的地方

沒有人會在設計區塊底下打initial

initial主要是用在模擬區塊的

再來

always @({in3, in2, in1, in0})

case( {in3, in2, in1, in0} )

2'd0: out = 1111110;

...endcase這裡

. 沒全貼了 你自己看你程式碼

這也有點錯誤

使用case包住四個輸入

基本上

她是等於4個bit

換個角度想 2bit如何表示9個數字

所以

改成這樣

always @(*) (*表所有)

case( {in3, in2, in1, in0} )

4'd0: out = 1111110;

4'd1: out = 0110000;

4'd2: out = 1101101;

4'd3: out = 1111001;

4'd4: out = 0110011;

4'd5: out = 1011011;

4'd6: out = 0011111;

4'd7: out = 1110000;

4'd8: out = 1111111;

4'd9: out = 1110011;

default: out = 7'bx;

endcase

再來就是模擬區塊了

寫成這樣

module tes;

wire out;

reg in0,in1,in2,in3;

IC_7447 test (in3, in2, in1, in0, out)

initial

begin

out = 0;

#10 {in3, in2, in1, in0} = 4'd0;

#10 {in3, in2, in1, in0} = 4'd1;

#10 {in3, in2, in1, in0} = 4'd2;

#10 {in3, in2, in1, in0} = 4'd3;

#10 {in3, in2, in1, in0} = 4'd4;

#10 {in3, in2, in1, in0} = 4'd5;

#10 {in3, in2, in1, in0} = 4'd6;

#10 {in3, in2, in1, in0} = 4'd7;

#10 {in3, in2, in1, in0} = 4'd8;

#10 {in3, in2, in1, in0} = 4'd9;

#10 \$finish;

end

這樣程式就寫完囉

所以全部 ..

module IC_7447(in3, in2, in1, in0, out);

input in0, in1, in2, in3;

output reg [6:0] out;

always @(*)

case( {in3, in2, in1, in0} )

4'd0: out = 1111110;

4'd1: out = 0110000;

4'd2: out = 1101101;

4'd3: out = 1111001;

4'd4: out = 0110011;

4'd5: out = 1011011;

4'd6: out = 0011111;

4'd7: out = 1110000;

4'd8: out = 1111111;

4'd9: out = 1110011;

default: out = 7'bx;

endcase

endmodule

module tes;

wire out;

reg in0,in1,in2,in3;

IC_7447 test (in3, in2, in1, in0, out)

initial

begin

out = 0;

#10 {in3, in2, in1, in0} = 4'd0;

#10 {in3, in2, in1, in0} = 4'd1;

#10 {in3, in2, in1, in0} = 4'd2;

#10 {in3, in2, in1, in0} = 4'd3;

#10 {in3, in2, in1, in0} = 4'd4;

#10 {in3, in2, in1, in0} = 4'd5;

#10 {in3, in2, in1, in0} = 4'd6;

#10 {in3, in2, in1, in0} = 4'd7;

#10 {in3, in2, in1, in0} = 4'd8;

#10 {in3, in2, in1, in0} = 4'd9;

#10 \$finish;

end

再加油吧

有問題再提出

很高興為你解答 ^^

2010-12-18 09:21:32 補充：

拍謝

module tes;

wire out;

reg in0,in1,in2,in3;

IC_7447 test (in3, in2, in1, in0, out)

initial

begin

out = 0;

這裡有點打錯了

wire out;這裡

out = 0;

這條不用打

把這條去掉就會正確囉

參考資料： 我/北科網管/北科電子大三生
• 匿名使用者
6 年前

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• 1 0 年前

參考看看吧!!

錯誤修改:

1. input reg in0, in1, in2, in3;

2. always @({in3, in2, in1, in0})

3. 2'd0: out = 1111110;

2'd1: out = 0110000;

2'd2: out = 1101101;

2'd3: out = 1111001;

2'd4: out = 0110011;

2'd5: out = 1011011;

2'd6: out = 0011111;

2'd7: out = 1110000;

2'd8: out = 1111111;

2'd9: out = 1110011;

module test(in3, in2, in1, in0, out);

input in0, in1, in2, in3;

output reg [6:0] out;

always @(in3, in2, in1, in0)

case( {in3, in2, in1, in0} )

2'd0: out = 7'b1111110;

2'd1: out = 7'b0110000;

2'd2: out = 7'b1101101;

2'd3: out = 7'b1111001;

2'd4: out = 7'b0110011;

2'd5: out = 7'b1011011;

2'd6: out = 7'b0011111;

2'd7: out = 7'b1110000;

2'd8: out = 7'b1111111;

2'd9: out = 7'b1110011;

default: out = 7'bx;

endcase

endmodule

2010-12-16 17:16:33 補充：

依據下面的大大的解答

case要修改成以下的樣子就OK囉!!

4'd0: out = 7'b1111110;

...

2'd9: out = 7'b1110011;

default: out = 7'bx;

如果沒打上7'b的話compile會判斷成"常數"而不是"二進制"

祝您成功 :)

參考資料： me