Fdhsdf 發問時間： 電腦與網際網路程式設計 · 9 年前

# verilog HDL LED燈做變化的問題...急

,抱歉,我實在是對Verilog一竅不通,請好心人幫幫忙,謝謝

### 2 個解答

• Smith
Lv 4
9 年前
最佳解答

module LED_CTL (

LED ,

DIP ,

CLK_2Hz,

RST_n

);

output [15:0] LED ; // assume high active

input [ 7:0] DIP ;

input CLK_2Hz;

input RST_n ;

reg [15:0] LED ;

reg [ 3:0] T ;

reg [ 3:0] T_next;

always @(posedge CLK_2Hz or negedge RST_n) begin

if (!RST_n) begin

T <= 0;

end else begin

T <= T_next;

end

end

always @* begin

if (T <= 12)

T_next = T + 1;

else

T_next = 0;

end

// according to your description: DIP[7:2] = 6'b101011

always @* begin

case (T)

0 : LED = {15'b0000_0000_0000_000, DIP[2]};

1 : LED = {DIP[7], 15'b000_0000_0000_0000};

2 : LED = {14'b0000_0000_0000_00, DIP[3], DIP[2]};

3 : LED = {DIP[7], DIP[6], 14'b00_0000_0000_0000};

4 : LED = {13'b0000_0000_0000_0, DIP[4], DIP[3], DIP[2]};

5 : LED = {DIP[7], DIP[6], DIP[5], 13'b0_0000_0000_0000};

6 : LED = {12'b0000_0000_0000, DIP[5], DIP[4], DIP[3], DIP[2]};

7 : LED = {DIP[7], DIP[6], DIP[5], DIP[4], 12'b0000_0000_0000};

8 : LED = {11'b0000_0000_000, DIP[6], DIP[5], DIP[4], DIP[3], DIP[2]};

9 : LED = {DIP[7], DIP[6], DIP[5], DIP[4], DIP[3], 11'b000_0000_0000};

10: LED = {10'b0000_0000_00, DIP[7], DIP[6], DIP[5], DIP[4], DIP[3], DIP[2]};

11: LED = {DIP[7], DIP[6], DIP[5], DIP[4], DIP[3], DIP[2], 10'b00_0000_0000};

default: LED = 16'b0000_0000_0000_0000;

endcase

end

endmodule

• 匿名使用者
6 年前

到下面的網址看看吧