Verilog 問題 不好意思,想請教一下Verilog到底要怎麼寫?? 以下是2對1多工器的寫法,內容我都看得懂,但是唯一不懂的就是,為什麼要這樣寫? 上網爬過很多文了,但就是沒有我要的答案,麻煩了!謝謝?

module Mux2_1( In1, In2, Sel, Out );

input In1, In2, Sel;

output Out;

wire In1, In2, Sel;

reg Out;

always @( In1, In2, Sel ) begin

if( !Sel )

Out <= In1;


Out <= In2;



1 個解答

  • 3 年前


    The designers of Verilog wanted a language with syntax similar to the C programming language, which was already widely used in engineering software development. Like C, Verilog is case-sensitive and has a basic preprocessor (though less sophisticated than that of ANSI C/C++). Its control flow keywords (if/else, for, while, case, etc.) are equivalent, and its operator precedence is compatible with C. Syntactic differences include: required bit-widths for variable declarations, demarcation of procedural blocks (Verilog uses begin/end instead of curly braces {}), and many other minor differences. Verilog requires that variables be given a definite size. In C these sizes are assumed from the 'type' of the variable (for instance an integer type may be 8 bits).

    A Verilog design consists of a hierarchy of modules. Modules encapsulate design hierarchy, and communicate with other modules through a set of declared input, output, and bidirectional ports. Internally, a module can contain any combination of the following: net/variable declarations (wire, reg, integer, etc.), concurrent and sequential statement blocks, and instances of other modules (sub-hierarchies). Sequential statements are placed inside a begin/end block and executed in sequential order within the block. However, the blocks themselves are executed concurrently, making Verilog a dataflow language.

    Verilog's concept of 'wire' consists of both signal values (4-state: "1, 0, floating, undefined") and signal strengths (strong, weak, etc.). This system allows abstract modeling of shared signal lines, where multiple sources drive a common net. When a wire has multiple drivers, the wire's (readable) value is resolved by a function of the source drivers and their strengths.

    A subset of statements in the Verilog language are synthesizable. Verilog modules that conform to a synthesizable coding style, known as RTL (register-transfer level), can be physically realized by synthesis software. Synthesis software algorithmically transforms the (abstract) Verilog source into a netlist, a logically equivalent description consisting only of elementary logic primitives (AND, OR, NOT, flip-flops, etc.) that are available in a specific FPGA or VLSI technology. Further manipulations to the netlist ultimately lead to a circuit fabrication blueprint (such as a photo mask set for an ASIC or a bitstream file for an FPGA).



    Verilog was one of the first popular[clarification needed] hardware description languages to be invented.[citation needed] It was created by Prabhu Goel, Phil Moorby and Chi-Lai Huang and Douglas Warmke between late 1983 and early 1984.[2] Chi-Lai Huang had earlier worked on a hardware description LALSD, a language developed by Professor S.Y.H. Su, for his PhD work.[3] The wording for this process was "Automated Integrated Design Systems" (later renamed to Gateway Design Automation in 1985) as a hardware modeling language. Gateway Design Automation was purchased by Cadence Design Systems in 1990. Cadence now has full proprietary rights to Gateway's Verilog and the Verilog-XL, the HDL-simulator that would become the de facto standard (of Verilog logic simulators) for the next decade. Originally, Verilog was only intended to describe and allow simulation, the automated synthesis of subsets of the language to physically realizable structures (gates etc) was developed after the language had achieved widespread usage.

    Verilog is a portmanteau of the words "verification" and "logic".[4]


    With the increasing success of VHDL at the time, Cadence decided to make the language available for open standardization. Cadence transferred Verilog into the public domain under the Open Verilog International (OVI) (now known as Accellera) organization. Verilog was later submitted to IEEE and became IEEE Standard 1364-1995, commonly referred to as Verilog-95.

    In the same time frame Cadence initiated the creation of Verilog-A to put standards support behind its analog simulator Spectre. Verilog-A was never intended to be a standalone language and is a subset of Verilog-AMS which encompassed Verilog-95.

    Verilog 2001[edit]

    Extensions to Verilog-95 were submitted back to IEEE to cover the deficiencies that users had found in the original Verilog standard. These extensions became IEEE Standard 1364-2001 known as Verilog-2001.

    Verilog-2001 is a significant upgrade from Verilog-95. First, it adds explicit support for (2's complement) signed nets and variables. Previously, code authors had to perform signed operations using awkward bit-level manipulations (for example, the carry-out bit of a simple 8-bit addition required an explicit description of the Boolean algebra to determine its correct value). The same function under Verilog-2001 can be more succinctly described by one of the built-in operators: +, -, /, *, >>>. A generate/endgenerate construct (similar to VHDL's generate/endgenerate) allows Verilog-2001 to control instance and statement instantiation through normal decision operators (case/if/else). Using generate/endgenerate, Verilog-2001 can instantiate an array of instances, with control over the connectivity of the individual instances. File I/O has been improved by several new system tasks. And finally, a few syntax additions were introduced to improve code readability (e.g. always, @*, named parameter override, C-style function/task/module header declaration).

    Verilog-2001 is the version of Verilog supported by the majority of commercial EDA software packages.

    Verilog 2005[edit]

    Not to be confused with SystemVerilog, Verilog 2005 (IEEE Standard 1364-2005) consists of minor corrections, spec clarifications, and a few new language features (such as the uwire keyword).

    A separate part of the Verilog standard, Verilog-AMS, attempts to integrate analog and mixed signal modeling with traditional Verilog.


    Main article: SystemVerilog

    The advent of hardware verification languages such as OpenVera, and Verisity's e language encouraged the development of Superlog by Co-Design Automation Inc (acquired by Synopsys). The foundations of Superlog and Vera were donated to Accellera, which later became the IEEE standard P1800-2005: SystemVerilog.

    SystemVerilog is a superset of Verilog-2005, with many new features and capabilities to aid design verification and design modeling. As of 2009, the SystemVerilog and Verilog language standards were merged into SystemVerilog 2009 (IEEE Standard 1800-2009). The current version is IEEE standard 1800-2012.


    A simple example of two flip-flops follows:

    module toplevel(clock,reset);

    input clock;

    input reset;

    reg flop1;

    reg flop2;

    always @ (posedge reset or posedge clock)

    if (reset)


    flop1 <= 0;

    flop2 <= 1;




    flop1 <= flop2;

    flop2 <= flop1;



    The "<=" operator in Verilog is another aspect of its being a hardware description language as opposed to a normal procedural language. This is known as a "non-blocking" assignment. Its action doesn't register until after the always block has executed. This means that the order of the assignments is irrelevant and will produce the same result: flop1 and flop2 will swap values every clock.

    The other assignment operator, "=", is referred to as a blocking assignment. When "=" assignment is used, for the purposes of logic, the target variable is updated immediately. In the above example, had the statements used the "=" blocking operator instead of "<=", flop1 and flop2 would not have been swapped. Instead, as in traditional programming, the compiler would understand to simply set flop1 equal to flop2 (and subsequently ignore the redundant logic to set flop2 equal to flop1).

    An example counter circuit follows:

    module Div20x (rst, clk, cet, cep, count, tc);

    // TITLE 'Divide-by-20 Counter with enables'

    // enable CEP is a clock enable only

    // enable CET is a clock enable and

    // enables the TC output

    // a counter using the Verilog language

    parameter size = 5;

    parameter length = 20;

    input rst; // These inputs/outputs represent

    input clk; // connections to the module.

    input cet;

    input cep;

    output [size-1:0] count;

    output tc;

    reg [size-1:0] count; // Signals assigned

    // within an always

    // (or initial)block

    // must be of type reg

    wire tc; // Other signals are of type wire

    // The always statement below is a parallel

    // execution statement that

    // executes any time the signals

    // rst or clk transition from low to high

    always @ (posedge clk or posedge rst)

    if (rst) // This causes reset of the cntr

    count <= {size{1'b0}};


    if (cet && cep) // Enables both true


    if (count == length-1)

    count <= {size{1'b0}};


    count <= count + 1'b1;


    // the value of tc is continuously assigned

    // the value of the expression

    assign tc = (cet && (count == length-1));


    An example of delays:


    reg a, b, c, d;

    wire e;


    always @(b or e)


    a = b & e;

    b = a | b;

    #5 c = b;

    d = #6 c ^ e;


    The always clause above illustrates the other type of method of use, i.e. it executes whenever any of the entities in the list (the b or e) changes. When one of these changes, a is immediately assigned a new value, and due to the blocking assignment, b is assigned a new value afterward (taking into account the new value of a). After a delay of 5 time units, c is assigned the value of b and the value of c ^ e is tucked away in an invisible store. Then after 6 more time units, d is assigned the value that was tucked away.